HDL (hardware definition language) software simulators are at the center of traditional verification methodologies. Most engineering teams describe their design and testbench in HDL. HDL software simulators are then used to verify the design with the testbench. However, due to the rapid increase in complexity, it's becoming increasingly ineffective to verify large SOC designs using only an HDL software simulator. Because of this, our view of HDL simulation is blurring.

Where a system once was comprised of three-to-five independent ASICs, it is now assembled with additional functionality into a single system on a chip (SOC). For example, the Ultra Sparc-III processor has 29 million transistors, an integrated memory management unit, and is over five times larger than its predecessor. At this level of complexity, SOC designs become highly integrated, have numerous system interfaces, and perform a multitude of functions. Sophisticated test sequences are required for verification; the design often includes many sub-systems and blocks represented at multiple levels of abstraction. These factors dictate the need for a heterogeneous design environment capable of verifying hundreds of millions of cycles per test. For large SOC designs, HDL simulation alone is no longer sufficient for design and verification.

While HDL will remain the preferred language for describing system implementation for several years to come, it is not the ideal language for designing SOCs. Higher-level languages such as C++ and SDL (system design language) are better suited to capture the complexity of SOC designs. The performance of an abstract model enables rapid validation of system-level algorithms and functionality. In addition, the same abstract model can be used to begin system integration and software development earlier in the design process. Using co-modeling techniques, engineers can link abstract system models to the design implementation without incurring communication overhead. Co-modeling takes advantage of the inherent performance of abstract models running on a workstation and the high performance of hardware-assisted verification systems such as emulators and accelerators.

Another technique for handling design complexity is design reuse in the form of legacy or purchased intellectual property (IP). Using IP reduces design time and provides models for standard functions such as microprocessors and memories. However, using IP generates additional demands on the schedule for integration and verification. No matter what the source of the IP, questions of the integrity and quality of the IP within the new design are always present. Was the IP block integrated properly? Were interface protocols compliant? Did subsequent modifications affect the original functionality? Verifying the IP within the context of the SOC design is difficult because of reduced controllability and visibility.

Further complicating the issue is the need to accommodate the native modeling environment of the IP source. IP isn't always available as HDL source code. Extensions for software, hardware, as well as abstract and timing accurate models need to be incorporated into the verification environment. Consequently, instruction set simulators, hardware modelers, and C-based tools are becoming part of the verification environment.

Ultimately, design managers must convince themselves and their management that a design will function as specified when delivered in silicon. This is particularly difficult and involves a struggle between schedule constraints and exhaustive verification. A common approach deploys a bottom-up methodology using directed tests. Directed tests provoke specific design conditions and functionality with potent, targeted activity. Tools such as intelligent testbench generators and functional coverage monitors assist in the creation of directed tests by providing automation and feedback.

However, directed testing alone does not provide adequate verification coverage, it only validates specified functionality. What about functionality not specified? With the myriad interfaces and functionality in an SOC design, it's impossible to identify a comprehensive set of directed tests. To gain additional confidence, design teams use random and real world testing. Random tests such as arbitrary instruction sequences and random bus accesses can find state dependent errors. Real world tests consist of running software such as booting an operating system and running a software application, playing back captured real data as in the case of applying recorded satellite data to a digital video decoder, and running with target systems modeled in software or hardware. However these tests typically involve long verification sequences. High performance verification systems like emulators and accelerators provide substantial performance increases over software simulation solutions. Hardware-assisted tools are able to verify the exponential number of events generated by real world and random tests.

SOC verification demands the same amount of planning, resources, and sophistication as the SOC design itself. As SOC complexity grows, the ability to efficiently capture design, integrate IP, and verify system-level functionality breaks traditional HDL software simulation methodology. Verification is the critical success factor in achieving tight schedules and insuring correct design functionality. Successful design teams are changing their approach to SOC development by making design and verification a parallel process that is planned and resourced at the start of a project, and incorporates high performance hardware-assisted tools as well as other advanced modeling tools and techniques. The growing complexity of SOC design is changing the way designs are verified and our traditional definition of HDL simulation tools.

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